| Radar Signal Processor Design Using FPGA |
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Changhun Ha, Bojun Kwon, Mangyu Lee |
1Radar.PGM Research and Development Institute, Hanwha Systems
2The 3rd Research and Development Institute, Agency for Defense Development |
| FPGA를 이용한 레이더 신호처리 설계 |
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하창훈, 권보준, 이만규 |
1한화시스템(주) 레이다.PGM 연구소
2국방과학연구소 제3기술연구본부 |
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| Abstract |
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The radar signal processing procedure is divided into the pre-processing such as frequency down converting, down sampling, pulse compression, and etc, and the post-processing such as doppler filtering, extracting target information, detecting, tracking, and etc. The former is generally designed using FPGA because the procedure is relatively simple even though there are large amounts of ADC data to organize very quickly. On the other hand, in general, the latter is parallel processed by multiple DSPs because of complexity, flexibility and real-time processing. This paper presents the radar signal processor design using FPGA which includes not only the pre-processing but also the post-processing such as doppler filtering, bore-sight error, NCI(Non-Coherent Integration), CFAR(Constant False Alarm Rate) and etc. |
| Key Words:
Radar, Signal Processing, FPGA, System Generator, CFAR |
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