| Phase Noise Analysis of 2.4 GHz PLL using SPD |
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Myeoung-ho Chae, Jee-heung Kim, Beom-jun Park, Kyu-song Lee |
1The 2nd Research and Development Institute, Agency for Defence Development
2Electronic Warfare PMO, Agency for Defense Development |
| SPD를 이용한 2.4 GHz PLL의 위상잡음 분석 |
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채명호, 김지흥, 박범준, 이규송 |
1국방과학연구소 제2기술연구본부
2국방과학연구소 전자전체계단 |
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| Abstract |
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In this paper, phase noise analysis result for 2.4 GHz PLL(phase locked loop) using SPD(sample phase detector) is proposed. It can be used for high performance frequency synthesizer's LO(local oscillator) to extend output frequency range or for LO of offset PLL to reduce a division rate or for clock signal of DDS(direct digital synthesizer). Before manufacturing, theoretical estimation of PLL's phase noise performance should be performed. In order to calculate phase noise of PLL using SPD, Leeson model is used for modeling phase noise of VCO(voltage controlled oscillator) and OCXO(ovened crystal oscillator). After theoretically analyzing phase noise of PLL, optimized loop filter bandwidth was determined. And then, phase noise of designed loop filter was calculated to find suitable OP-Amp. Also, the calculated result of phase noise was compared with the measured one. The measured phase noise of PLL was -130 dBc/Hz @ 10 kHz. |
| Key Words:
Fixed PLL, SPD, Phase Noise, Loop Filter |
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