| Signal Processing Logic Implementation for Compressive Sensing Digital Receiver |
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Woohyun Ahn, Janghoon Song, Jongjin Kang, Woong Jung |
1EW R&D Center, Hanwha Systems
2Technical Sales Department, Xilinx Korea |
| 압축센싱 디지털 수신기 신호처리 로직 구현 |
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안우현, 송장훈, 강종진, 정웅 |
1한화시스템(주) 전자전연구센터
2자일링스 코리아 기술영업부 |
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| Abstract |
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This paper describes the real-time logic implementation of orthogonal matching pursuit(OMP) algorithm for compressive sensing digital receiver. OMP contains various complex-valued linear algebra operations, such as matrix multiplication and matrix inversion, in an iterative manner. Xilinx Vivado high-level synthesis(HLS) is introduced to design the digital logic more efficiently. The real-time signal processing is realized by applying dataflow architecture allowing functions and loops to execute concurrently. Compared with the prior works, the proposed design requires 2.5 times more DSP resources, but 10 times less signal reconstruction time of $1.024{mu}s$ with a vector of length 48 with 2 non-zero elements. |
| Key Words:
Compressive Sensing, Orthogonal Matching Pursuit, High-Level Synthesis, Complex Matrix Multiplication, Inverse Matrix |
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